Field of the Invention
With the ever-increasing speed of digital circuits comes the problem of running subcircuits at speeds in excess of their minimum requirements (e.g., not at their maximum performance capabilities), thus wasting system resources for power. Impedance controllers in particular, can perform functionally at or below 1 MHz. However, they are often incorporated into a system running at 500 MHz plus. Due to the nature of digital circuits, the impedance controller is forced to run off of the system clock or some division thereof. The clock speed is generally well above the speed needed by the controller. By running at higher speeds than is necessary, the power consuming portions of the circuit operate more frequently than is necessary, thereby wasting power. The main system clock can be slowed by dividing the system clock. However, dividing system clocks creates more system clocking issues and requires more power for the system.
Additionally, analog impedance control circuits can take up areas hundreds of times larger than those of their digital counterparts.
Therefore, there is a need for an impedance controller that operates digitally and that runs independently of the system clock. The invention described below provides such a controller that does not use the system clock, but instead updates as the impedance of the I/O drivers to match that of the off-chip circuit.
The present invention generally relates to impedance controllers and more particularly to an improved impedance controller that does not utilize a clock signal and, by being free of the clock signal, the invention can operate at its optimum speed independently of the clock signal of the device in which it is embodied.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional impedance controller, the present invention has been devised, and it is an object of the present invention to provide a structure for an impedance controller that does not rely upon any external clock signal and is free to operate at its optimum speed.
In order to attain the object(s) suggested above, there is provided, according to one aspect of the invention, an impedance controller that has an impedance control logic outputting an adjustable impedance and a comparator comparing the adjustable impedance with a reference voltage. The impedance control logic recalibrates the adjustable impedance only when the comparator indicates a change in impedance. The impedance control logic recalibrates the adjustable impedance independently of a system clock signal. The comparator comprises a dual differential amplifier comparator. The dual differential amplifier comparator includes a first differential amplifier comparator adapted to identify a high impedance and a second differential amplifier comparator adapted to identify a low impedance. The impedance controller has an alternating incremental impedance adjustment circuit adapted to converge the adjustable impedance and an inverse adjustable impedance to an amount less than the high impedance and greater than the low impedance, as controlled by the first differential amplifier and the second differential amplifier. The alternating incremental impedance adjustment circuit has a counter adapted to generate the adjustable impedance and an inverter adapted to generate the inverted adjustable impedance. The invention also has a plurality of latches adapted to temporarily hold the adjustable impedance. The inverted adjustable impedance and multiplexors select between increment values of the adjustable impedance and the inverted adjustable impedance until one of the adjustable impedance and the inverted adjustable impedance is substantially equivalent to the reference voltage. The impedance controller includes an enable signal that controls the multiplexors in incrementing values of the adjustable impedance and the inverted adjustable impedance.
Implementing the ideas contained in this invention could save power resources in systems using standard impedance controllers which run off system clocks or some division thereof. Secondly, this impedance controller circuit runs on demand when there is a change in impedance. Thus, it is idle a large percentage of the time. Finally, it saves designers from dealing with clock synchronization issues because the controller works off its own generated recalibration signal which does not need to be synchronous with a system clock. Systems that implement the design described within will also benefit from area savings. Since there are no clock tree circuits within the design, the area normally consumed by these circuits is available for additional system logic and added functionality. In systems with many impedance controllers on a system on a chip (SoC), the area savings become greater the more these improved impedance controllers replace traditional system clock driven controllers. In fact, any system that currently implements an impedance controller design could benefit from the use of this improved controller. Older designs could be reworked to implement the new impedance controllers and future designs could make these controllers the new standard.